Github Repositories Trend

pulp-platform/pulpino

An open-source microcontroller system based on RISC-V
Homepage
http://www.pulp-platform.org
Total stars
545
Stars per day
0
Created at
3 years ago
Language
C
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syntacore/scr1

SCR1 is an open-source RISC-V compatible MCU core
Total stars
207
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ucb-bar/rocket-chip

Rocket Chip Generator
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openwrt-mirror/openwrt

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Homepage
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Total stars
503
Language
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sergeykhbr/riscv_vhdl

VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".
Homepage
http://sergeykhbr.github.io/riscv_vhdl/
Total stars
235
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Total stars
546
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RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
Total stars
166
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Total stars
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Total stars
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